TSMC to Add a New 3nm Fab as AI Orders Pile up - The Information

TSMC's additional 3nm fab is not a capacity play—it is a structural lock-in on the EUV supply chain. ASML's delivery backlog already stretches to 2027; by absorbing more of that pipeline, TSMC raises the cost floor for Samsung and Intel to reach parity. The binding constraint shifts from node performance to equipment access. On compliance, the concentration of 3nm output in Taiwan, China has become the most visible vulnerability in Washington's resilience narrative. CHIPS Act subsidies are pivoting from incentivizing diversification to mandating replication. The Arizona 2nm timeline will increasingly be governed by political deadlines rather than engineering milestones. Strategically, Samsung's 3nm GAA yield remains below 60%, and Intel's 18A has slipped repeatedly. TSMC is exploiting the exact window where rivals are weakest—converting a 'who gets there first' race into a 'who can ship at scale' moat. The 18-month outlook: the bottleneck migrates from front-end lithography to CoWoS advanced packaging. AI compute delivery will be gated by interposer capacity, not transistor density. The real scarcity is no longer the chip—it is the package.