TSMC sees surging AI chip demand, highlights advanced packaging and physical AI opportunities

TSMC's signal here isn't about demand volume—it's about packaging capacity displacing process node as the binding constraint on AI compute. CoWoS-L and SoIC yield-ramp cycles, not EUV tool counts, will set the actual delivery ceiling for global AI silicon through 2026. Physical AI opens a second curve: embodied-intelligence edge inference chips (5-15nm, high efficiency, automotive-grade reliability) diverge structurally from datacenter HPC, forcing TSMC into strategic capacity-allocation trade-offs. On competition, Samsung's 2nm and Intel 18A are closing the gap, but the real structural threat comes from the OSAT tier. ASE and Amkor are elevating advanced packaging from a back-end service to a quasi-front-end capability, eroding TSMC's vertical-integration premium. Geopolitically, the Arizona fab's ramp trajectory determines whether US customers can decouple from the Taiwan, China supply chain, while equipment export-control compliance is already baked into roughly 3-5% of incremental capex. 18-month outlook: HBM4 chiplet integration and physical-AI-dedicated ASICs will be the two key variables for gross margin. Verdict: packaging is the new process node. Whoever owns the 3D-stacking yield curve owns AI-era pricing power.