TSMC said to mull making advanced AI memory chips - The Malaysian Reserve

TSMC's potential entry into AI memory chips is not a commodity DRAM play—it is a power grab over the logic base die in HBM4 and beyond. Today's HBM3E base dies are fabricated at 12-14nm by memory makers, but HBM4 will push toward 7nm/5nm, squarely in TSMC's wheelhouse. If TSMC bundles advanced logic with CoWoS packaging, SK Hynix and Samsung get demoted from design-plus-fab to stack-plus-test, and their margin pool is structurally compressed. The technical ripple runs deeper: the logic-memory boundary in AI accelerators is being redrawn. NVIDIA's HBM4 roadmap and AMD's MI400 will face a critical base-die supplier decision. If HBM5 converges on 3D hybrid bonding, the binary taxonomy of memory maker versus logic maker simply dies. On compliance, any US export-control expansion covering AI memory components would force TSMC's new business through CHIPS Act scrutiny and China-restriction review simultaneously, raising operational costs for its China-Taiwan fabs. Competitively, Samsung will accelerate 12nm GAA logic adoption for AI customers; SK Hynix may be forced to outsource base-die design, ceding core margin to its rival. Within 18 months, HBM4 yield qualification is the real inflection point. Whoever controls the advanced base-die process controls AI compute supply-chain pricing power.