TSMC’s latest chip packaging breakthrough promises lower costs and better performance - Digital Trends

Taiwan Semiconductor Manufacturing Company (TSMC) is making a significant leap in chip packaging with its new Chip-on-Panel-on-Substrate (CoPoS) technology, promising lower manufacturing costs and imp... Read original →

TSMC’s CoPoS isn’t just a packaging tweak—it’s a strategic pivot that redefines performance economics for AI chips. By shifting from circular wafers to rectangular panels, TSMC boosts material efficiency and enables larger chiplet assemblies critical for NVIDIA’s next-gen accelerators, directly countering the soaring costs of 3nm EUV scaling. This forces upstream equipment makers to retrofit panel-handling capabilities and pushes system designers to overhaul thermal/power delivery. Geopolitical friction amplifies supply chain fragility, especially around temporary glass carriers, likely triggering dual-sourcing mandates. While ASE and Samsung push FOPLP and I-Cube, TSMC’s CoWoS/CoPoS tandem maintains its lead—but yield ramp by 2027 remains uncertain. Over the next 18 months, every 10% increase in AI package area will drive 15% higher capex in substrates and test infrastructure. Packaging is now the new frontier of Moore’s Law.