TSMC's AI-fuelled profit streak hits sixth straight record in 3Q26, but 2nm expansion weighs on margins

TSMC's sixth consecutive record quarter masks a structural pivot: the volume-for-margin trade-off inherent in 2nm ramp. Per-wafer costs run roughly 40% above the 5nm node, while AI customers' bargaining power shifts toward CoWoS advanced packaging — the true bottleneck has migrated from lithography to interconnect capacity. Technology cascade: 2nm GAA architecture doubles EUV layer requirements, compressing equipment depreciation from five years to 3.5, directly eroding gross margins. If Apple transitions to 2nm in 2027, consumer and AI workloads will compete for identical production lines — an unprecedented capacity collision. Compliance exposure: domestic capacity in Taiwan, China faces power and water allocation ceilings; the Arizona 2nm line, if operational by 2027, adds 15-20% per-wafer cost. This is not risk hedging; it is a structural margin concession. Competitive dynamics: Samsung's 2nm GAA, if it reaches volume production in Q4 2026, gains eligibility for NVIDIA's next-gen inference silicon, breaking TSMC's single-source dominance in AI accelerators. Intel's 18A foundry push could carve a niche in 2.5D packaging. 12-24 month outlook: AI demand shifts from training arms-race to inference-scale deployment. 2nm's marginal value declines; the 3nm/5nm cost-performance band becomes the battleground. TSMC's moat is migrating from process leadership to packaging plus ecosystem lock-in. The margin ceiling is visible now.