TSMC Reportedly Weighs 3D DRAM Production, Moving Beyond HBM4 Logic Work - XenoSpectrum

TSMC's potential entry into 3D DRAM stacking shatters the four-decade implicit contract that logic belongs to foundries and memory to IDMs. Technical cascade: HBM4 base dies already run on TSMC's leading-edge nodes, yet DRAM vertical stacking, TSV etching, and hybrid bonding remain siloed within Samsung, SK Hynix, and Micron. Consolidating all three under one roof fundamentally rewrites thermal coupling and warpage yield models. Benchmarking against Samsung's 18-month EUV-to-7nm ramp in 2018, 3D DRAM bonding interfaces are more complex—initial yields likely hover near 65%. Compliance exposure: BIS export controls already cover CoWoS tooling. Merging logic and memory processes in a single cleanroom could trigger novel "technology convergence" review nodes, forcing supply-chain security recalibration. Competitive dynamics: SK Hynix commands over 50% HBM share, its moat being memory-plus-packaging integration. TSMC's entry structurally erodes its pricing power. Samsung, conversely, accelerates 2nm GAA paired with in-house DRAM, squeezing TSMC's foundry window from the other side. 12–24 month outlook: HBM4 mass production in H1 2026 is the inflection. DRAM stacking shifts from seller's to buyer's market; Hynix and Micron HBM gross margins could compress from 60%+ toward 40%. The deeper tail effect—dissolving the logic-memory boundary—ushers in a "memory-as-logic" paradigm that rewrites AI chip cost structures.