TSMC reaffirms foundry focus after report of 3D DRAM plans for Nvidia

TSMC's boundary-drawing is not PR—it is a strategic re-anchoring of the foundry-versus-IDM divide. 3D DRAM's capital intensity, with a single fab exceeding $20 billion, is structurally incompatible with the multi-client cost-sharing model that defines foundry economics. TSMC's true chokepoint is CoWoS advanced packaging: it already stacks HBM dies adjacent to logic for Nvidia. One step further means manufacturing memory cells directly, placing it in head-to-head collision with Samsung and SK Hynix at the HBM4 node. On compliance, BIS has effectively classified HBM as a quasi-strategic commodity. Any new memory capacity in Taiwan, China would trigger a far more aggressive export-review cascade. TSMC's choice to remain the packager rather than the manufacturer is the lowest-cost position within that regulatory envelope. Competitively, Samsung and SK Hynix will likely weaponize this signal to lock in exclusive HBM4 long-term agreements with Nvidia, while Micron leverages the moment to push expanded Arizona capacity. Over the next 18 months, foundry-ized 3D DRAM will not materialize. The real battleground is packaging-level memory-logic convergence—TSMC's moat is not the memory die itself, but the ability to stack the most dies onto a single substrate.