TSMC races to expand AI chip capacity while CPO and CoWoS move to center stage - digitimes

TSMC is accelerating AI chip capacity expansion to meet growing global demand for artificial intelligence computing power. At NVIDIA's GTC Taipei conference, CEO Jensen Huang delivered a packed keynot... Read original →

TSMC’s rush to scale 3nm and sub-3nm capacity isn’t just about transistors—it’s converting process leadership into a throughput moat. The co-evolution of CPO and CoWoS is forcing optical module suppliers to redesign packaging stacks and GPU architects to embrace heterogeneous integration, shifting competition from pure lithography to system-level bandwidth density. Geopolitically, TSMC’s Taiwan, China-centric supply chain, while currently optimized for NVIDIA, faces escalating compliance overhead if U.S. export controls tighten or hyperscalers mandate localized Chiplet ecosystems. Samsung and Intel will aggressively pitch ‘de-Taiwanized’ alternatives to Meta and AWS, especially in 2.5D/3D packaging, likely triggering price wars. Within 18 months, advanced packaging capacity—not wafer starts—will be the true bottleneck. If TSMC fails to sustain CoWoS yields above 90% and open its ecosystem beyond NVIDIA, its AI dominance could fracture structurally.