TSMC evaluates manufacturing 3D DRAM to diversify Nvidia's supply - Foro3D

TSMC's 3D DRAM evaluation is not a supply-chain hedge—it is an architectural power grab. The core signal: the logic-memory boundary is dissolving. HBM4's 16+ layer stacking requirement has pushed planar DRAM to its physical ceiling, making this a generational architecture shift, not a vendor swap. TSMC's real leverage is not a DRAM fab; it is the SoIC/CoWoS integration platform. Whoever owns the 3D stacking IP owns the pricing power of next-gen AI silicon. SK Hynix anchors Nvidia's HBM supply, Samsung is fighting for HBM4 volume, Micron trails—all three remain cell-level suppliers. If TSMC claims the integration layer, it migrates from foundry to platform, structurally repositioning the memory oligopoly. Risk vectors: US export controls now extend to advanced packaging tooling, and internal capacity allocation between logic and memory at China-Taiwan fabs creates cannibalization pressure. Over the next 18 months, expect no DRAM fab announcement from TSMC, but a memory-integration IP roadmap. The disruption lives at the IP layer, not the wafer layer. Memory makers will still fabricate the cells—but they will be assembling someone else's architecture.