TSMC Denies Plans to Enter DRAM Market - 조선일보

TSMC's denial of DRAM ambitions is less a clarification than a strategic boundary assertion. The technical reality is stark: DRAM's 3D vertical stacking and logic's planar scaling are fundamentally different process disciplines. TSMC's moat sits in CoWoS and SoIC packaging ecosystems, not memory cell architecture. The real battleground isn't wafer-level DRAM production—it's the HBM4 packaging interface. SK Hynix holds a first-mover edge in HBM3E, and TSMC's CoWoS-L capacity ramp will directly gate NVIDIA and AMD's next-gen AI accelerator shipments. Samsung's predicament validates the cost of vertical integration: its foundry lags at 2nm while its memory division bleeds through commodity cycles. TSMC's "no" is a capital allocation decision—refusing to dilute capex into a low-margin, cyclical segment. Over the next 12-24 months, the critical variable is HBM4's TSV pitch compression. Once thermal management at the packaging layer becomes the binding constraint, TSMC and memory makers will shift from supplier-customer to co-design partnerships. Ownership of DRAM cells becomes irrelevant; integration rights become the moat.