TSMC Denies DRAM Market Entry, Affirms Foundry Focus - 조선일보

TSMC's explicit refusal to enter DRAM is not a business boundary statement—it is a structural confirmation of the global memory power triopoly. Technically, HBM manufacturing remains locked within Samsung, SK Hynix, and Micron. But the real battleground has shifted: through CoWoS-L and SoIC packaging, TSMC has become the de facto "system-level adhesive" between HBM stacks and AI accelerators. Compute-memory separation is not converging; it is hardening due to advanced packaging complexity. The compliance dimension is more revealing. The CHIPS Act's underlying logic protects Micron's domestic U.S. memory capacity. TSMC crossing into DRAM would have shattered Washington's "de-risking" narrative. This denial is, in essence, a calibrated geopolitical signal: I will not touch your memory pie; keep feeding me leading-edge logic orders. On the competitive front, Micron's Idaho expansion now carries a more certain ROI profile, while Samsung is likely to redirect capex toward HBM4, accelerating share erosion of SK Hynix. Over the next 12–24 months, DRAM manufacturing will settle into oligopolic equilibrium. The genuine variable is CXL memory-architecture standardization—whoever controls the "memory pooling" interface definition bypasses the manufacturing moat and redistributes profit at the system layer. TSMC's "non-entry" paradoxically creates the strategic whitespace for this deeper architectural contest.