TSMC CoWoS prices may rise up to 20%, report says - NeoTeo

The 20% CoWoS price hike is not a routine cost adjustment—it is a structural repricing of advanced packaging as the new strategic chokepoint in AI compute. When B200 and MI300X die-to-die interconnect density hits physical limits, silicon interposer area and HBM stack layers become the performance ceiling. Packaging has effectively absorbed the post-Moore compute increment. The price shock propagates bidirectionally through the BOM: upstream ABF substrate, TSV etching, and micro-bump material suppliers gain pricing leverage; downstream AI ASIC designers see margins compressed, with Broadcom and Marvell's custom silicon most exposed. As CoWoS-L scales toward larger reticle sizes, yield cost curves have not converged—20% is likely a floor, not a ceiling. Competitively, Intel's EMIB and Samsung's I-Cube see their catch-up windows narrow further. In a capacity-constrained regime, customers will not switch suppliers, which paradoxically entrenches TSMC's oligopoly pricing power in 2.5D packaging. ASE lacks front-end silicon interposer synergy and cannot meaningfully divert volume near-term. 12-24 month outlook: AI chip dependency on CoWoS deepens. The hike will force customers to lock 2026-2027 capacity long-term agreements and accelerate SoIC 3D stacking to bypass 2.5D area constraints. Pricing power in advanced packaging is migrating irreversibly from the wafer fab to the packaging node.