TSMC CoWoS output reportedly to reach at least 200K wafers in 2027 - digitimes

TSMC is accelerating advanced packaging capacity expansion to address persistent supply constraints. Market reports indicate that the company's CoWoS (Chip on Wafer on Substrate) monthly output is pro... Read original →

TSMC’s push to scale CoWoS output to 200K wafers/month by 2027 isn’t just capacity expansion—it’s a foundational shift in AI infrastructure. Technically, this forces EUV and temporary bonding equipment suppliers to accelerate innovation, while pressuring OSATs to pivot toward chiplet-based integration. Downstream, NVIDIA gains relief from H100/B100 bottlenecks but becomes further locked into TSMC’s packaging ecosystem. Geopolitically, despite U.S. CHIPS Act subsidies for its Arizona fab, critical materials remain concentrated in Taiwan, China—any disruption risks global AI chip lead times. Samsung and Intel will counter with I-Cube and Foveros, yet yield and ramp delays leave them 18+ months behind. Within 24 months, advanced packaging will evolve from a performance enhancer to a market-entry prerequisite, sidelining any HPC player lacking heterogeneous integration capability.