TSMC Could Charge Up to 20% More for CoWoS Packaging Amid AI Crunch - TechPowerUp

The 20% CoWoS price hike is not a supply squeeze—it is a structural repricing of where value accrues in the AI silicon stack. Drawing the parallel to 2018's DRAM supercycle, where Samsung and SK Hynix extracted 40%+ premiums, TSMC's leverage here is even more rigid: the binding constraint for every major AI accelerator is no longer lithography but advanced packaging throughput. Technically, the silicon interposer area ceiling on CoWoS-L caps 2.5D stacking yield, forcing Broadcom and Marvell to re-architect chiplet roadmaps around packaging constraints rather than die performance. On the competitive front, Intel's Foveros and Samsung's I-Cube remain 18-24 months behind in volume yield and customer trust—no credible near-term diversion exists. Over the next 12-24 months, expect two acceleration curves: hyperscalers front-loading capex into in-house packaging lines, and TSMC compressing the CoWoS-to-SoIC generational transition to lock in standard-setting authority. The deeper implication: packaging's share of AI chip BOM will climb from roughly 8% to 15%+, fundamentally re-slicing the profit pool across the compute supply chain. TSMC is no longer just a foundry—it is the pricing authority for the AI era.