TSMC CEO says profitability has no ceiling, plans High-NA EUV adoption in 2030

Wei's "no ceiling on profitability" is not optimism—it's a pricing-power declaration. When NVIDIA and AMD accelerator roadmaps are entirely anchored to N3/N2 wafers, foundry has shifted from cost center to profit engine. This is structural monopoly economics, not a cyclical upswing. Technically, 2030 High-NA EUV adoption locks ASML's 0.55 NA tool as the sole path below 1nm. At $350M+ per unit, compounded by Cymer light-source and Zeiss optics delivery bottlenecks, capex barriers jump another order of magnitude. Photoresist and mask-blanket qualification cycles run 18-24 months, making 2027 the critical positioning window. On competition: Samsung's 2nm GAA and Intel's 18A trail by 12-18 months in yield, but the real battleground has moved off the die. CoWoS advanced packaging and HBM stacking are the actual AI-chip bottlenecks. If TSMC expands packaging capacity by 30%, rivals' "process catch-up" narratives dissolve into ecosystem lock-in. 12-24 month tail effects: AI capex tilts toward HBM and advanced packaging, structurally lifting foundry gross margins past 60%. Meanwhile, Taiwan, China's geographic position turns any equipment delivery delay into a systemic single-point-of-failure risk. This isn't a "challenge"—it's an existential dependency.