TSMC CEO outlines efforts to enhance cost-effectiveness of High-NA EUV - Crypto Briefing

TSMC's CEO outlined efforts to improve the cost-effectiveness of High-NA EUV lithography, despite its $400 million price tag, which is double that of previous-generation EUV tools. While TSMC has acqu... Read original →

TSMC’s deliberate delay in deploying High-NA EUV for volume production reflects a calculated bet on the inflection point of lithography economics. By extending low-NA EUV through multi-patterning, it curbs depreciation burdens and reduces strategic vulnerability to ASML’s pricing power. This decision cascades upstream—forcing photoresist, mask, and EDA vendors to recalibrate R&D roadmaps for sub-2nm nodes. Geopolitically, U.S.-backed incentives are pushing Intel and SK Hynix into premature High-NA adoption, risking capital inefficiency if yield ramps falter. Over the next 18 months, TSMC’s restraint could pressure ASML to accelerate cost-optimized successors while granting Chinese equipment makers critical breathing room to fortify alternative ecosystems in mature-node manufacturing.