TSMC, ASML and Imec push 2D transistors toward manufacturing

The integration of 2D-material CMOS transistors on 300mm wafers by imec, ASML, and TSMC (Taiwan, China) is not a lab curiosity—it’s a strategic stake in the post-Moore scaling race. Technically, it forces co-evolution of EUV patterning, atomic-layer deposition, and dry-transfer processes, especially demanding breakthroughs in gate dielectrics and contact resistance. From a compliance angle, if 2D channels skirt existing silicon-based export controls, the U.S. BIS may classify them as 'advanced channel materials,' raising long-term supply chain costs. Competitors like Samsung and Intel will likely double down on oxide semiconductors or CFET to avoid dependency on this emerging ecosystem. Within 18 months, while mass production remains distant, this capability will become a critical bargaining chip for equipment vendors vying to define sub-3nm standards—who sets the 2D integration rules will dictate pricing power in the next era.