TSMC 3D DRAM report linked to Nvidia draws response ... - eeNews Europe

TSMC coupling 3D DRAM stacking with Nvidia's AI accelerators is not a packaging upgrade—it is a structural reallocation of value. When TSV, hybrid bonding, and logic-memory vertical integration all sit under one foundry roof, the traditional three-tier chain (memory maker + foundry + OSAT) collapses into two, and the OSAT layer gets systematically devalued. For Nvidia, 3D DRAM shifts the HBM4 bottleneck from cell density to stack height and bonding yield—exactly where TSMC's SoIC/CoWoS ecosystem holds a structural edge. But this concentrates supply-chain risk on a single node in Taiwan, China. Under the current US export-control regime, any technology transfer involving advanced memory stacking could trigger BIS scrutiny, pushing compliance costs onto both parties. Samsung and SK Hynix will almost certainly accelerate in-house HBM4 stacking within 12 months to retain memory sovereignty. The problem: AI memory walls demand 5 nm logic layers coupled with 12+ DRAM tiers, and memory makers' own advanced-logic nodes cannot keep pace. Over the next 24 months, "who owns the 3D stacking process" will replace "who owns DRAM IP" as the core bargaining chip in the AI compute supply chain.