TLB develops SOCAMM3 substrates; Vietnam plant to break ground

The strategic weight of SOCAMM3 substrate development lies not in the "next-gen" label but in the brutal arithmetic of inference-side bandwidth-per-watt. With HBM for training locked into a three-player oligopoly, the memory interface for inference workloads has become the new value anchor. TLB's 2028 mass-production target is effectively a race to own the 2025-2027 customer qualification window—its two anchor clients almost certainly map to SK Hynix and Samsung, and that relationship determines whether TLB migrates from commodity module substrates into the advanced-packaging substrate tier. The Vietnam groundbreaking is a textbook jurisdictional hedge. Multi-layer lamination and fine-line fabrication face equipment export-control constraints; shifting capacity to Southeast Asia compresses regulatory exposure but adds 6-12 months to yield ramp and imposes rigid localization demands on upstream copper foil and ABF resin supply. On competition, Unimicron (Taiwan, China) and Ibiden have built first-mover moats in AI server substrates. TLB's wedge is vertical depth in memory-module-specific design—whichever player first validates 20+ layer stacking for SOCAMM3 locks in BOM share for the next inference platform generation. The 12-24 month tail: SOCAMM2 capacity expansion will erode DDR5 substrate margins, while SOCAMM3 qualification cadence will dictate the memory-interface standard for 2027 AI inference silicon. Substrates are no longer a supporting role—they are the invisible bottleneck defining compute efficiency.