TIER IV joins JST's Next-Generation Edge AI Semiconductor R&D Program to open-source AI chip designs for autonomous driving - The Manila Times

On August 14, 2026, the Japan Science and Technology Agency (JST) launched a next-generation edge AI semiconductor research and development program, into which TIER IV, a leading company in autonomous... Read original →

TIER IV’s participation in JST’s next-gen edge AI chip R&D signals a pivotal shift from closed to open ecosystems in autonomous driving hardware. By leveraging Transformer-based architectures and TOSA, this initiative accelerates performance gains in 3nm EUV chips, challenging GPU dominance in edge inference. The move stimulates upstream EDA vendors and forces downstream system integrators to restructure their tech strategies. Amid geopolitical shifts, Chinese Taiwan and Hong Kong suppliers may face compliance dilemmas. Competitors like NVIDIA and Qualcomm are likely to accelerate proprietary chip development and open-source initiatives to counter this trend. Within 12–24 months, modular, multi-vendor chip designs will dominate the edge AI landscape, accelerating L4 autonomous driving commercialization.