The pioneer behind TSMC's FinFET leap: a personal look at Chenming Hu

Chenming Hu's FinFET work at Berkeley wasn't incremental—it was a paradigm detour around the physical ceiling of 2D planar transistors. The downstream impact is structural: Applied Materials had to fundamentally re-architect its etch and deposition toolsets from "planar patterning" to "3D structural precision," reshaping the entire equipment capex cycle. The competitive read is sharper. Intel's 10nm stumble was, at its core, an architectural hesitation during the FinFET-to-GAA transition. TSMC in Taiwan, China, by locking down N2 GAA yield windows, has reset the process-node gap from "quarterly" back to "annual" territory. Samsung's aggressive SF2 bet is a positional play against TSMC's GAA yield curve, not a technology leap. Twelve to twenty-four months out: CFET is moving from white paper to PDK. Equipment vendors will face a "4D processing" demand wave, triggering the next capex supercycle. The deeper signal: the academic-to-fab conversion cycle is compressing from a decade to three-to-five years. The talent arms race is escalating from headhunting to co-built lab ecosystems. That's a moat deeper than any lithography tool.