The landscape of chip manufacturing has been reshaped. - 36Kr

The structural reset in chip manufacturing is not about who fabricates wafers—it is about who controls the nodes. The center of gravity is shifting from lithography to advanced packaging and critical materials. Technical cascade: With GAA architectures at full scale, EUV exposure steps jump from 50+ at 3nm to 80+ at 2nm, structurally amplifying ASML's pricing leverage. More critically, CoWoS and SoIC have graduated from back-end processes to the core bottleneck for compute density. The 2025 global CoWoS capacity gap still exceeds 30%, making packaging scarcer than wafers themselves. Compliance and risk: Export controls have stretched equipment lead times from six to 18+ months. Firms now maintain dual-track supply chains, adding roughly 20% in hidden compliance costs per die. The geographic concentration of leading-edge capacity in Taiwan, China forces customers into a pay-premium-for-security pricing paradigm. Market dynamics: If Intel's 18A ships on schedule by late 2025, it shatters TSMC's exclusive 2nm window. Samsung is hedging via HBM4 plus SoIC differentiation rather than head-on node competition. SMIC's 28-to-14nm capacity expansion is quietly resetting the global pricing anchor for mature nodes. Twelve-to-twenty-four-month outlook: Expect extreme bifurcation—starvation at the leading edge, structural glut at mature nodes. Industry capital efficiency will decline 15-25%. The variable that defines 2026's competitive landscape is not who hits 1nm first, but who locks in advanced packaging capacity allocation first.