The data wall, not power, is AI's real constraint: ScaleFlux's CXL bet - Dealroom

ScaleFlux's CXL wager is less a product bet than a paradigm challenge: the binding constraint in AI is not FLOPS or watts, but data access latency. If that holds, the capital logic that funneled roughly 40% of data-center spend into liquid cooling and power infrastructure over the past three years needs recalibration. Technically, CXL elevates memory from a chip-attached commodity to a poolable, shareable resource layer, directly eroding the HBM pricing moat held by SK Hynix and Samsung. As CXL 3.0 shared-memory architectures partially bypass bandwidth ceilings, Astera Labs and other controller vendors capture structural upside while memory makers face margin compression. Supply-chain risk is real: CXL controllers and high-speed SerDes IP remain concentrated in a handful of US and Taiwan, China firms. Tightening export controls could hollow out the "open standard" label, forcing dual-sourcing strategies before the market matures. Competitively, NVIDIA's NVLink closed ecosystem and CXL's open route are structurally incompatible. If ScaleFlux demonstrates that memory pooling cuts per-token inference cost by 30%+, AMD and Intel will accelerate CXL 3.1 platform adoption, and NVIDIA will be pressured to embed a compatibility layer in its next-gen architecture. Over the next 12–24 months, AI infrastructure investment will pivot from stacking compute to moving data. Memory vendors' business models will shift from selling dies to selling bandwidth. Whoever controls data flow controls the pricing power of the inference economy.