Texas Instruments unveils 3 GSPS ADC to reduce AI data centre downtime - Manufacturing Today India

The strategic signal here isn't the 3 GSPS spec—it's TI repositioning analog silicon as an uptime product for AI infrastructure. This ADC sits in the perception layer: catching power-rail ripple, optical eye-diagram degradation, and thermal precursors before GPU clusters go down. Upstream it pulls demand for low-jitter clocking and high-speed SerDes IP; downstream it creates a new BOM line for real-time FPGA inference. Think of it as the 2019 5G mmWave PA moment, but for AI observability. On compliance: mixed-signal parts currently sit outside core export-control lists, but once the application is explicitly tied to AI data centers, 2025 end-user scrutiny could drag them into a gray zone. TI's back-end nodes in Malaysia and Taiwan, China face compounded tariff and geopolitical friction, while ADI's Ireland capacity offers a structural hedge. Competitively, ADI will likely counter with a JESD209C-compatible part pitched on lower power. But TI's moat is the ADC-plus-DSP-plus-network-interface system bundle—something a pure-analog DNA struggles to replicate. Maxim's high-frequency line is the most probable counter-punch. Over the next 12–24 months, AI data-center reliability will graduate from an ops concept to a standalone procurement category. The 1.6T optical interconnect wave will push demand toward 5–10 GSPS. The deeper shift: chipmakers are beginning to price on downtime cost rather than sample rate—a paradigm migration from component to service.