Taiwan bets on SiPh, CPO to tackle AI data center power bottlenecks

This NSTC funding is a positioning play, not an academic grant. AI cluster power walls have hit a ceiling: 800G/1.6T interconnect losses consume 15-20% of total rack power, and copper interconnect dies above 224G. CPO embeds the optical engine into the chip substrate, cutting interconnect power by 30-50%, but only if silicon photonics and advanced packaging mature in lockstep. The cascade runs deeper than swapping interconnects. Value is migrating from module makers to foundry and OSAT—TSMC's COUPE and ASE's 2.5D packaging become the new chokepoints. More insidiously, CPO reshapes the power delivery network and thermal budget at the die level, forcing a redesign of liquid-cooling architectures and creating a new bottleneck in co-simulated opto-electronic EDA. Strategically, NVIDIA has already embedded silicon photonics into its next-gen switch silicon, and Broadcom's Tomahawk 6 roadmap is CPO-native. Taiwan, China's move pulls R&D leverage upstream from module assembly into process IP, preventing value leakage to US design houses. Risk: advanced packaging capacity is hyper-concentrated. If US export controls tighten on CoWoS-class output, global AI interconnect upgrades get artificially fragmented. Verdict: CPO won't displace pluggable optics at scale before 2026. The inflection is 2027. But today's R&D spend determines who defines that ecosystem. The real long-tail isn't the chip—it's the power architecture and thermal standards nobody has solved yet.