Synopsys extends partnership with Samsung Foundry to support AI and multi-die chip designs - Data Center Dynamics

Synopsys and Samsung Foundry have extended their partnership to enhance Synopsys’ portfolio of AI-powered EDA tools, certified interface IP, and silicon test capabilities, aimed at accelerating the ti... Read original →

The Synopsys–Samsung Foundry alliance is less about innovation and more a survival tactic against the exploding complexity of AI chip design at 2nm. Technically, AI-augmented EDA flows and multiphysics signoff are forcing upstream IP reuse models to evolve, pulling packaging and test into early design phases to close the ‘design-manufacturing-validation’ loop. On compliance, tighter tool certification within Samsung’s ecosystem mitigates U.S. export control risks on advanced-node EDA access—especially for customers in Taiwan, China and mainland China. Competitively, this pressures Cadence’s position in Samsung’s stack and will likely accelerate TSMC’s partnerships with Ansys and Siemens EDA to defend its multi-die leadership. Over the next 18 months, EDA vendors must transition from point-tool suppliers to pre-silicon validation platforms—or risk irrelevance as fragmented IP players without full-stack integration get squeezed out.