Synopsys 112G Linear PHY IP: OIF-CEI-112G-LINEAR-PAM4 Compliance for AI - News and Statistics - IndexBox

Synopsys has launched a 112G linear PHY IP compliant with the OIF-CEI-112G-LINEAR-PAM4 standard, tailored for high-speed data transmission in AI applications. As AI models grow in complexity, the dema... Read original →

Synopsys’ launch of 112G PAM4 PHY IP marks a pivotal step in high-speed interconnects for AI data centers. This advancement directly impacts upstream EDA toolchains and downstream server/AI chip manufacturers, who must align their designs to meet escalating bandwidth demands. Compliance with OIF-CEI standards enhances supply chain coherence but increases reliance on IP vendors. Competitors like Cadence and Mentor Graphics are likely to accelerate product development to maintain market relevance. In the medium term, this move will drive standardization across AI infrastructure, especially amid intensifying U.S.-China tech rivalry. The technology is poised to become a key performance differentiator, with more chipmakers adopting it within 12–24 months, pushing the entire ecosystem toward higher frequency and advanced modulation schemes.