South Korea's 300mm research gap: Daejeon pitches an open fab as a US$1.46 billion fix

Korea's semiconductor bottleneck was never capacity—it's knowledge diffusion. Samsung and SK Hynix own memory, but the country lacks a neutral 300mm shared R&D platform where fabless designers and university labs can iterate advanced nodes without absorbing a $20B proprietary fab cost. Daejeon's $1.46B proposal is, in substance, an "imec for the Korean peninsula": decoupling process exploration from commercial production. Technically, an open demo fab creates a feedback loop for EDA validation, advanced packaging, and materials screening. Upstream, ASML and Applied Materials gain a research-grade anchor. Downstream, Korea's structurally weak IP design ecosystem gets a 5nm-class tape-out path, reducing structural dependence on TSMC and SMIC. But the open-access architecture is the critical vulnerability: process recipes circulating across multiple tenants erode the proprietary moat sustaining Samsung's and SK Hynix's memory dominance. Both will almost certainly withhold core IP. US export controls on EUV further cap the practical node ceiling near 7nm. Strategically, the real competitors are Intel's IDM 2.0 open foundry and TSMC's Arizona R&D ecosystem. A successful "neutral platform" positioning would siphon fabless design wins from TSMC's orbit. 12–24 month outlook: equipment pre-orders within six months of approval; meaningful wafer output no earlier than 2027. The decisive variable is Samsung's participation. Absent that, this becomes a well-funded university lab—impressive in policy documents, irrelevant to the $500B global foundry market.