Industry Analysis
SK hynix's 20x AI infrastructure growth projection is less a demand forecast than a capacity-anchoring signal within the HBM oligopoly.
Technical cascade: The HBM3E-to-HBM4 transition pushes TSV stacking from 12 to 16-24 layers, inflating DRAM die area per GPU by 30-40%. Upstream, ASML EUV and Applied Materials bonding equipment become the binding constraint. Downstream, NVIDIA's B200/GB300 bandwidth hunger forces SK hynix to cannibalize general-purpose DDR5 capacity at P4/P5 fabs, triggering a structural DRAM price spike in 2025Q3-2026Q1.
Compliance exposure: US BIS restrictions on HBM2E+ exports to China have already severed 15-20% of SK hynix's incremental addressable market. A deeper risk: if Washington extends controls to CoWoS packaging, SK hynix's advanced-packaging collaboration with TSMC (Taiwan, China) faces decoupling pressure, potentially adding 20%+ to per-unit HBM yield costs.
Competitive dynamics: Samsung trails by one quarter on HBM3E yield but is betting aggressively on MR-MUF for HBM4. Micron locks short-term share via its exclusive NVIDIA HBM3E deal. SK hynix's true moat is customer-design-cycle depthβjoint architecture definition with NVIDIA, AMD, and Broadcom for next-gen ASICs.
12-24 month outlook: HBM enters an extreme seller's market. But watch H2 2026: if inference-side demand decelerates from exponential to linear, the 18-24-month fab buildout cycle will create a 2019-NAND-style inventory glut. Anchor median expectations at 8-12x, not 20x.
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