SK Hynix's New York chip plans hit snag over US restrictions on China, sources say - The Korea Times

The New York snag is not a bureaucratic hiccup—it is the structural collision between Washington's build-domestic mandate and its own export-control architecture. SK Hynix, commanding over 50% of the HBM market, cannot decouple its fab from ASML EUV, Lam etch, and Shin-Etsu wafer supply chains. A single entity-list touchpoint anywhere in that stack triggers simultaneous BIS and CFIUS scrutiny, converting a capital project into a multi-year compliance labyrinth. The technical stakes are concrete: HBM4 TSV stacking demands ultra-pure precursors and sub-nanometer alignment. A six-to-nine-month review delay compresses the 2026 delivery window for NVIDIA B200 and AMD MI400 accelerators, handing Micron—America's only domestically clean memory maker—a policy tailwind to accelerate HBM3E customer migration. Samsung's Taylor, Texas site gains parallel geopolitical leverage with hyperscaler buyers. If SK Hynix is forced to downgrade the New York site from full wafer fabrication to back-end packaging, its global HBM cost structure rises 8–12% permanently. Over the next 12–24 months, expect BIS to compress the de minimis threshold from 25% toward 10%, compelling every Asian memory player operating in the US to maintain dual-track supply chains. Annualized compliance overhead will swell by $1.5–2 billion industry-wide. The memory sector is irreversibly shifting from efficiency-optimal to security-redundant logic.