SK hynix projects AI infrastructure performance to grow 20-fold by 2030 - The Korea Times

SK hynix's "20x AI infrastructure performance by 2030" projection is less a forecast than a capacity-locking signal to its supply chain. The 20x math points to a compound of HBM stack density (8→16→24 layers), hybrid bonding yield, and CoWoS-class packaging bandwidth—not merely node shrinking. Within 24 months, TSV etch equipment and hybrid bonding lines will become scarcer bottlenecks than EUV lithography itself. On compliance, the December 2024 US export control update places HBM3E and above under review; SK hynix's Wuxi packaging facility faces elevated "technology spillover" audit risk, with operating costs likely rising 15-20% as it restructures across Taiwan, China and US supply chains. Competitively, Samsung is racing to certify its 16-layer HBM4 for NVIDIA's next platform window, while Micron sidesteps head-on bandwidth wars via CXL 3.0 memory pooling. SK hynix's true moat isn't a single process node—it's the co-design iteration depth with NVIDIA and AMD, a design lock-in far stickier than leading by one generation. The 12-24 month tail: customized HBM (bandwidth-to-capacity ratios tuned for specific inference silicon) will displace commodity specs as the dominant SKU. Memory vendors are migrating from standard component suppliers to compute architecture co-designers—a structural repositioning that rewrites the P/E multiple applied to the sector.