SK hynix HBF: A New Memory Class Between HBM and SSD - igor´sLAB

HBF is not a "new memory class"—it is SK hynix's structural repricing of the NAND value chain. When AI inference workloads land in the dead zone between HBM's cost curve and SSD's latency floor, stacking 3D NAND with HBM-like interconnects forcibly injects DRAM-grade bandwidth premiums into the flash segment. The technical ripple hits two axes. TSV and micro-bump processes migrate from DRAM-exclusive to NAND-compatible, forcing OSAT players to recalibrate roadmaps. NAND bonding precision now tracks DRAM specs, reshaping order flows at Applied Materials and Lam Research. Compliance risk is non-trivial. If BIS expands advanced-packaging export controls to cover NAND stacking, SK hynix's Dalian fab faces immediate upgrade constraints. The 2023 EUV restrictions already proved equipment chokepoints are more lethal than chip-level bans. Strategically, Samsung is the most dangerous counterparty. Its V-NAND and HBM3E synergy maps naturally onto HBF, with 1.5× the capacity of SK hynix. Micron will likely skip HBF entirely, betting on HBM4 and letting rivals cannibalize each other. Within 12–24 months, HBF debuts in inference accelerators, roughly 2–4 units per board. The true long-tail effect: NAND pricing logic shifts from capacity-per-GB to bandwidth-per-TB·s. Pure-play NAND vendors unable to follow the stacking curve will be squeezed out of the AI memory supply chain by 2027.