Silicon Photonic Modulator Reaches 200 Gb/s PAM4 With Reduced DSP (Science Tokyo, Yokohama, AIST, PETRA)

The 200 Gb/s PAM4 headline is table stakes. The real signal is analog-domain equalization displacing DSP. In AI cluster interconnects, DSP consumes 35–40% of transceiver power. Pushing equalization into a slow-light silicon modulator with an integrated EO equalizer fundamentally rewrites the power and BOM equation for 800G/1.6T modules. Technical ripple: design complexity migrates from DSP silicon (Broadcom, Marvell) to the photonic IC, eroding the "DSP-defines-everything" architecture that anchored the 400G/800G era. Downstream, lower thermal load accelerates CPO adoption; upstream, the analog front-end becomes the new IP moat while InP laser demand stays flat. Competitive read: Intel, Coherent, and Lumentum are all chasing 200G/lane, but an analog-first philosophy collides head-on with Broadcom's DSP-centric margin structure. PETRA—a startup—validating this path signals the barrier is lower than the market assumes, compressing the catch-up window for mid-tier module makers. 12–24 month trajectory: expect 1.6T module architectures to embed analog pre-equalization, cutting DSP lane counts from 4×200G toward 2×200G. Japan's university–AIST–startup pipeline mirrors the MEMS sensor playbook: niche precision first, then 30% global share within three years.