Siemens’ Tessent software enables direct test pattern execution over PCIe and USB - New Electronics

Siemens is not adding a port — it is migrating test-execution authority from ATE hardware into the software layer. For two decades, advanced-node chip testing has been locked into proprietary channels on Teradyne or Advantest platforms. Routing patterns over PCIe/USB breaks that dependency for the first time. The ripple effects cut across the stack. Upstream, DFT IP becomes the true value center: once the execution channel is commoditized, differentiation collapses into pattern-generation algorithms and coverage optimization. Midstream, ATE vendors' high-margin test services face structural erosion; OSAT players in Taiwan, China (ASE, Amkor) will see their test-phase bargaining power diluted. Downstream, chip designers gain unprecedented agility — particularly for chiplet architectures, where per-die verification no longer requires board-level equipment. The risk vector is non-trivial. Test patterns are architectural fingerprints. Transmitting them over general-purpose buses widens the IP-leakage surface and will force export-control reviews to operate at finer granularity. Twelve-to-twenty-four-month outlook: Cadence and Synopsys will be compelled to ship counter-features. ATE hardware will contract into calibration and extreme-condition niches. "Software-defined test" is about to become the new battleground in EDA.