Siemens Extends Tessent Test Flow to Pattern Execution Over PCIe - EE Times Asia

This is not a feature update—it is a structural migration of the test boundary from die-level to system-level interconnect. At PCIe Gen6's 64GT/s PAM4 signaling, conventional ATE scan tests cannot cover protocol-layer timing or LTSSM state-machine transitions. Tessent's pattern execution over PCIe effectively shifts verification left: link training, CXL interop sequences, and equalization convergence now execute in pre-tapeout simulation. This directly erodes the value anchor of Keysight and Tektronix in interconnect test equipment, and forces Synopsys and Cadence to accelerate coupling between their verification IP and DFT flows. On compliance: single-vendor lock-in in the test toolchain is a structural vulnerability under export-control regimes. OSATs in Taiwan, China (ASE, PTI) deeply coupled to Tessent workflows face prohibitive switching costs if licensing is restricted—risk more insidious than the chip IP itself. Competitive response: Synopsys will likely embed more aggressive PCIe LTSSM accelerators in VCS; Cadence will differentiate via Xcelium+ModSim. The real variable is PCI-SIG's interop certification bar—whoever closes the design-verify-certify loop first owns Gen6/CXL 3.0 test authority. Outlook: within 12-24 months, die-to-die interconnect testing under chiplet architectures becomes the new bottleneck. Tessent's PCIe move is the overture, not the main event. Test-as-a-Service will erode traditional ATE revenue; Keysight's P&L structure faces re-rating by 2027.