Siemens extends NVIDIA AI collaboration for automated 3D IC electrothermal design workflows - EE Times Asia

The Siemens-NVIDIA push to embed AI into 3D IC electrothermal simulation is not a feature update; it is a paradigm break. EDA is migrating from parameterized software to a compute-algorithm hybrid. In vertically stacked architectures, thermal pathways are physically severed, and classical FEM solvers hit a hard ceiling at million-transistor densities. AI surrogate models compress verification from weeks to hours, rewriting the design economics of CoWoS, Foveros, and I-Cube. Upstream, GPU clusters become mandatory EDA infrastructure, structurally raising the entry barrier for smaller fabless players. Downstream, HBM4 and chiplet heterogeneous integration cadences accelerate. Synopsys (Ansys) and Cadence face a 12-month window to deploy comparable AI-native simulation stacks or cede pricing power in advanced packaging verification. On compliance, if AI model weights enter export-control lists, the shock path mirrors the 2022 EDA tool restrictions. Packaging foundries in Taiwan, China and mainland design houses will absorb the highest switching costs. Within 24 months, expect an AI-compute-driven M&A consolidation wave. The valuation logic shifts decisively: compute consumption replaces license counts as the new moat metric.