Siemens EDA Says AI Can Cut Chip Design Time by Up to 10x - thelec.net

Siemens EDA unveiled at a media briefing in Seoul, South Korea, that its latest artificial intelligence (AI) technology can reduce chip design time by up to tenfold. According to Ankur Gupta, Senior V... Read original →

Siemens EDA’s introduction of multi-agent AI technology, capable of reducing chip design time by a factor of ten, marks a paradigm shift in semiconductor design workflows. This innovation exerts significant pressure on upstream EDA toolchains, especially in RTL design and verification stages, accelerating the obsolescence of legacy tools. Integration with NVIDIA’s Nemotron models enhances trust in verification processes, setting new standards for design integrity. Downstream chip designers will face increased demands for AI-enabled platforms, reshaping traditional design practices. Geopolitically, this advancement intensifies U.S.-China competition in semiconductor technologies, particularly in EDA tools, heightening supply chain risks involving Taiwan, China. If Synopsys and Cadence fail to rapidly integrate AI, they risk losing market leadership. Within the next 12 months, AI-driven design tools will become industry standard, with verification automation becoming the key differentiator in competitive positioning.