Siemens and Samsung Foundry strengthen collaboration to advance silicon design enablement - Siemens

Siemens has announced an expanded collaboration with Samsung Foundry to advance semiconductor design and manufacturing workflows for the global fabless ecosystem. The partnership emphasizes the deploy... Read original →

Siemens’ deepened alliance with Samsung Foundry is a defensive move against runaway yield and verification risks at 3nm/2nm nodes. Technically, Calibre and Aprisa’s real-time EUV error compensation will redefine design rule decks for fabless firms, while Tessent’s AI-driven DFT slashes silicon validation cycles by ~30%. Geopolitically, tightening U.S.-EU export controls on advanced lithography gear compel Samsung to certify non-U.S. EDA stacks, mitigating supply chain rupture risks. In response, Synopsys and Cadence will likely escalate IP bundling—especially around HBM3E and CoWoS alternatives. Within 18 months, this partnership will accelerate the industry’s shift from ‘design-assist’ to ‘manufacturing-defined’ EDA paradigms, spurring foundries in Taiwan, China and mainland China to fast-track indigenous EDA ecosystems to reduce Western tool dependency.