SiC MOSFETs cut switching losses and resistance - EDN - Voice of the Engineer

The simultaneous compression of switching loss and on-resistance in SiC MOSFETs marks a paradigm shift from adequate to extreme efficiency in power semiconductors. The ripple extends far beyond the device: 8-inch substrate yield is now the binding constraint, and the capacity race between Wolfspeed and mainland China/Taiwan, China substrate makers will anchor post-2026 cost curves. Downstream, 800V DC architectures in AI data centers and the EV platform migration to 800V are converting SiC from optional to mandatory, leaving silicon IGBTs fewer than 18 months of commercial relevance. On compliance, CHIPS Act subsidies and export controls create a paradox—U.S. SiC fabs capture capital tailwinds, yet substrate feedstock and epitaxy equipment remain exposed to single-point supply failures. Chinese players (SICC, TanKeBlue) are weaponizing aggressive 6-inch pricing; if 8-inch yields break through, global SiC device ASPs could drop another 15-20% by H2 2025, directly compressing Infineon's and ST's margins. The decisive variable over the next 24 months is not technology but capacity ramp velocity and 800V standardization speed. SiC is completing its identity shift from niche to infrastructure—and the first casualties will be second-tier power device houses still betting on silicon.