SEMICON Europa 2026 puts advanced packaging and AI in focus ... - eeNews Europe

When process scaling hits the 2nm physical wall, packaging stops being a back-end step and becomes the true battleground for compute supremacy. SEMICON Europa 2026 elevating advanced packaging alongside AI is no coincidence—CoWoS capacity, HBM stacking, and chiplet interconnect are now scarcer than EUV lithography tools. The technical cascade is severe: HBM4's 16-high stacks demand TSV yield and underfill formulations that compress supplier R&D cycles to under 12 months. ABF substrate makers face capacity lock-in from AI orders well before 2027. On compliance, the EU Chips Act mandates doubled local production by 2030, yet hybrid-bonding and TCB equipment from BESI and ASMPT still route through Taiwan, China and Japan supply chains. European fabs will absorb a 15-25% hidden premium on equipment procurement due to export-control reviews. Strategically, TSMC's CoWoS-L ramp pace directly gates AMD MI400 and NVIDIA Rubin delivery windows. Intel's EMIB, if it clears 95% yield by Q3 2026, becomes the first credible volume alternative. ST and Infineon are positioning as the "neither-US-nor-China" packaging node, leveraging policy tailwinds. Outlook 12-24 months: UCIe 2.0 standardization will cut cross-die interconnect costs by roughly 40%, shifting packaging from bespoke craft to platformized product. Whoever owns the core IP in hybrid bonding—BESI, ASM International—will wield pricing power exceeding front-end toolmakers.