Samsung to use TSMC technology for Nvidia’s next-generation memory chips, Seoul newspaper reports - WTVB

This isn't a foundry partnership—it's a structural admission. HBM4's logic base die is migrating to sub-5nm nodes, and Samsung's logic fab simply cannot compete with TSMC (Taiwan, China) at 3nm or below. When Nvidia's next-gen AI accelerators demand a logic layer at that node, Samsung's in-house logic line is a non-starter. This is a capability gap being outsourced, not a strategic alliance. The technical ripple is profound: HBM4 dissolves the old boundary between memory and logic. The base die now carries ECC, SerDes PHY, and scheduling logic at SoC-level complexity. HBM5 may embed micro-NPUs. If Samsung keeps sourcing its logic layer externally, its vertical-integration moat erodes against SK Hynix's tighter TSMC coupling. Compliance exposure: delivery cadence becomes hostage to Taiwan, China's capacity scheduling, while export controls on EUV tools narrow Samsung's logic expansion window. Squeezed between the HBM volume race and logic dependency, margin compression hits hard in 2026. Competitive response: SK Hynix will lock in TSMC for HBM4 logic while qualifying GlobalFoundries as a second source. Micron bets on full-stack in-house, pairing 1β DRAM with proprietary controllers. Twelve to twenty-four months out, "memory chip" as a category ceases to exist. It becomes a logic-plus-memory-plus-advanced-packaging composite. Samsung's AI memory share slides from leader to second tier unless its logic gap closes by 2026.