Samsung to use TSMC tech for Nvidia's next-generation memory chips, says Seoul newspaper - The Business Times

Samsung's decision to route Nvidia's next-gen memory through TSMC's packaging is a structural admission: its I-Cube advanced packaging cannot independently meet HBM4's interconnect density and thermal thresholds. Handing bare dies to CoWoS lines demotes Samsung from vertically integrated player to a memory-die vendor — the most significant strategic concession in its semiconductor portfolio since the 2010s. On compliance, cross-licensing packaging IP between direct competitors sits in a gray zone under BIS export controls. TSMC's fabs rely on US-origin equipment and EDA tools; the audit chain spans Seoul, Taiwan, China, and the US. A single policy tightening at any node risks severing the entire chain. Competitively, SK Hynix already holds deep CoWoS capacity allocations, so Samsung's move erodes its differentiation. Micron gains a geopolitical premium via Amkor's US-based packaging. TSMC escalates from foundry to packaging oligarch, with bargaining power over both memory giants growing non-linearly. Over the next 12–24 months, the HBM4 production window (H2 2025–2026) will be the stress test. Expect Samsung to accelerate in-house packaging R&D or qualify a second supplier to dilute TSMC dependency. Nvidia, meanwhile, will likely push full decoupling of memory, logic, and packaging stacks, platformizing the packaging layer. The endgame isn't who makes the die — it's who controls the packaging bottleneck.