Samsung to use TSMC’s 3nm process for Nvidia’s next-gen HBM chips - Communications Today

Samsung outsourcing its HBM base-die logic to TSMC's 3nm GAA node is a quiet admission that its in-house SF3 process cannot deliver the SerDes density and leakage profile HBM4 demands. This shatters the 'memory maker builds everything in-house' paradigm and shifts the competitive axis from stack height to base-die logic sophistication. The supply chain now threads through three jurisdictions: DRAM dies in Korea, logic base die in Taiwan, China, and final integration in the US. Any export-control tightening at any node in this chain can strangle the entire HBM pipeline. Worse, TSMC's 3nm capacity is already oversubscribed by Apple, AMD, and Qualcomm — Samsung's HBM base die sits at the bottom of the allocation queue, ceding pricing power. SK Hynix, commanding the majority of Nvidia's HBM3E volume, will likely deepen its TSMC logic partnership and widen the generational gap. Micron, still fighting HBM3E qualification, may find a narrow window in the mid-tier segment. Within 18 months, HBM base dies become a de facto TSMC product category. The 'memory foundry' boundary dissolves. Samsung's moat narrows from full-stack capability to DRAM-die fabrication and packaging, while TSMC's TAM expands into memory-interface logic. This is a structural re-cutting of the semiconductor division of labor.