Samsung speeds P5 Fab 2 construction as memory chip shortage looks to last through 2028

Samsung locking P5 Fab 2 structural work to January 2027 is not a capacity play—it is a pre-emptive strike in the HBM supply war. The ripple effect cascades well beyond the Pyeongtaek campus: ASML's EUV delivery windows compress further, Shin-Etsu and SUMCO shift 12-inch wafer allocations ahead to Q4 2026, and TSMC's CoWoS advanced-packaging slots become the true chokepoint where Samsung and SK Hynix will contest HBM shipment share. On the compliance front, the Pyeongtaek site sidesteps US onshore-build geopolitical friction, yet EUV tool exports remain firmly under BIS jurisdiction. Any escalation in China-bound technology screening will stretch equipment lead times and inflate per-wafer cost. More critically, with HBM still a three-player oligopoly, Samsung's acceleration sharply raises the probability of an HBM3E price war by H2 2026, while Micron's Idaho ramp—underwritten by CHIPS Act subsidies—creates a two-front squeeze on margins. My 18-month call: memory is transitioning from cyclical boom-bust to a structurally tight equilibrium driven by AI inference demand. If the 2028 shortage materializes, HBM4's 16-high stacking will define the next competitive frontier. The depreciation burden from this capex supercycle will bleed into 2030 and beyond. There is no exit ramp on this buildout.