Samsung chief Lee visits Japan chip packaging lab - The Korea Herald

Lee Jae-yong's hands-on visit to a Japanese packaging facility signals something far more consequential than a routine R&D tour. As EUV lithography hits diminishing returns, advanced packaging has quietly become the true compute bottleneck. Samsung is hunting a differentiated edge in HBM4 and CoWoS-L — Japan controls irreplaceable nodes in TSV bonding materials, ABF substrates, and hybrid bonding processes that no single rival can replicate. On compliance, the 2023 US-Japan export-control alignment has tightened the noose. Anchoring packaging capacity in Japan rather than Taiwan, China is a deliberate geopolitical hedge, pushing Samsung's supply-chain diversification from planning into execution. The cost premium — roughly 15-20% per packaged unit from higher labor and energy — buys export certainty that no volume discount can offset. Competitively, TSMC's CoWoS allocation stretches into 2026 while Intel's Foveros Direct lags on yield. If Samsung locks in hybrid-bonding yield advantages in Japan, the 2026 HBM4 window crystallizes into a packaging-level standoff: Samsung-NVIDIA versus TSMC-AMD. 12-24 month call: packaging becomes the second chokepoint after wafer foundry. Industry valuation logic shifts from process node to packaging capacity multiplied by yield.