Samsung And TSMC Foundry Cuts Push 8-Inch Chip Capacity Utilisation Towards 90% - Electronics For You BUSINESS

Samsung and TSMC's synchronized 8-inch capacity reduction is not a production cut—it is a strategic abandonment. The 90% utilization target is a deliberate oligopoly pricing mechanism: artificial supply constraints guarantee 20-30% ASP premiums on remaining lots. The technical ripple is severe. 8-inch wafers underpin power management ICs, analog circuits, MCUs, and increasingly SiC devices. Fabless automotive and industrial customers face a binary choice: migrate to 12-inch (doubling NRE, adding 6-12 months of qualification) or absorb price hikes and extended lead times. Equipment vendors like Lam Research and Applied Materials will see 8-inch tool orders collapse, leaving only service contracts as residual revenue. The geopolitical dimension is the real story. Both the US CHIPS Act and EU Chips Act channel subsidies exclusively toward 12-inch advanced nodes. 8-inch becomes a regulatory orphan—no strategic priority, no public funding. This accelerates geographic bifurcation: Hua Hong's 120k wpm 8-inch expansion is perfectly positioned to absorb displaced demand. The global mature-node supply chain is splitting along a 12-inch-stays-West, 8-inch-shifts-East axis. Over 12-24 months, 8-inch enters managed decline. Global wafer starts share compresses from roughly 30% to 15-20%. SiC 1200V devices set a demand floor, but the ceiling is locked. UMC (Taiwan, China) and GlobalFoundries capture near-term overflow, but the structural winner is China's mature-node ecosystem.