Samsung 2nm push gains momentum as Synopsys cuts NPU die area by 22% - digitimes

Recent progress in the collaboration between Samsung and Synopsys highlights advancements in advanced chip manufacturing. Synopsys achieved a 22% reduction in die area for a neural processing unit (NP... Read original →

The collaboration between Samsung and Synopsys marks a significant leap in advanced chip design and manufacturing integration. Synopsys’ Fusion Compiler tool achieved a 22% die area reduction for an NPU using Samsung’s SF2P 2nm process, validating the maturity of Samsung’s advanced node and highlighting the critical role of design tools in performance optimization. This advancement accelerates the adoption of NPUs in data centers and edge computing, where efficiency and scalability are paramount. From a supply chain perspective, this development may prompt global semiconductor firms to reassess their technology roadmaps, especially amid intensified U.S.-China tech decoupling. The Chinese Taiwan/ Taiwan, China and U.S. rivalry in high-end manufacturing is intensifying, and early adoption of such synergies could erode competitive advantages of rivals like TSMC and UMC. Within the next 12 months, the convergence of design tools and advanced processes will define competitive dynamics, signaling a dual shift toward higher design efficiency and manufacturing precision.