Rumored Intel Nova Lake table lists three 'BFC' chips with up to 144MB of L3

Intel's rebranding of bLLC to BFC and the 144MB L3 ceiling signal a strategic pivot: in AI inference workloads, cache bandwidth has overtaken core count as the primary performance determinant. This is not a spec-sheet exercise. At 144MB, chiplet die area expands significantly, making EMIB/Foveros packaging yield the single point of failure. Intel's dependency on advanced packaging capacity in Taiwan, China deepens accordingly. Upstream, this cache volume forces a redesign of memory controllers and HBM interface bandwidth, triggering a new capex cycle for photomask, substrate, and advanced packaging suppliers. On the competitive front, AMD's EPYC 9004 already ships with 256MB shared L3. Intel's move reads as defensive catch-up, not offense. The deeper structural threat: once on-package cache crosses the 100MB threshold, the architectural boundary between CPU and GPU begins to dissolve, eroding x86's moat in AI inference. 12-24 month projection: BFC architecture will force Intel Foundry to accelerate 18A node ramp to amortize packaging costs, or gross margins will erode. On the software side, Linux kernel cache scheduling and hypervisor memory management will undergo a quiet but fundamental rewrite. That silent software-layer revolution is where the real long-tail impact lives.