Recommendations on the proposal for a Chips Act 2.0 - Teknologiateollisuus ry

Finland's Teknologiateollisuus lobbying on Chips Act 2.0 signals a structural pivot: the EU is shifting from subsidy-driven fab construction to ecosystem lock-in via standards and IP governance. The tech-stack implication is fundamental. Act 1.0 measured success in wafer starts; 2.0 will almost certainly reweight toward advanced packaging, chiplet interconnect standards (UCIe), and EDA sovereignty. Finland's downstream angle—telecom and industrial automation—exposes the real policy pain point: it is no longer lithography capacity but design-to-verification cycle time and IP provenance traceability. Compliance exposure is the hidden cost. A 'trusted design origin' clause would stack US export controls atop EU data-sovereignty audits, pushing per-chip compliance overhead up 15-25% for multinational fabless players. With ASML's High-NA delivery slots booked through 2027, any mandatory local verification layer stretches lead times further. Strategic positioning: Washington's CHIPS Act has anchored Intel and TSMC (Taiwan, China) capacity; Beijing's Big Fund III targets mature nodes and equipment localization. If Brussels plays 'standards architect' rather than 'capacity competitor,' ASML and Siemens EDA capture the largest alpha, while TSMC and Samsung arbitrage across three competing subsidy regimes. 12-24 month outlook: expect the first EU 'strategic chip' list (automotive MCUs, industrial FPGAs, comms modems) and an intensifying legislative fight over chiplet interconnect. The industry is entering a three-pole standards war.