Rapidus, HCLTech launch 2 centres to advance semiconductor engineering - Evertiq

Rapidus-HCLTech's dual centers are the third structural piece of a de-China semiconductor closed loop: US capital, Japanese fabrication, Indian design talent. The two facilities almost certainly anchor design verification and process-software co-optimization, with HCLTech's simulation and systems-integration capability embedded directly into Rapidus's 2nm PDK development (targeting 2027-2028 volume production). Technical cascade: Synopsys and Cadence face diluted pricing power upstream; downstream OSAT players face integrated design-fab competition. Compliance exposure is acute — IP flowing across Japan, India, and US jurisdictions triggers layered BIS export controls and India's data-localization mandates. Any 2nm process parameter crossing borders risks entity-list-level scrutiny. Competitive response: TSMC will likely accelerate internalization of its Design Enablement ecosystem; Samsung will deepen India design penetration. The structural variable is more consequential — if this model scales, India replicates the Bangalore design-hub pattern across nodes, directly pressuring Silicon Valley's design-outsourcing market. 12-24 month trajectory: By H2 2025 into 2026, Rapidus should ship first 2nm PDK beta, with HCLTech verification teams functioning as de facto internal staff. The deeper implication: a Japan-India semiconductor axis emerges independent of US-EU frameworks, and the EDA market's oligopoly structure faces its first genuine disruption by 2027.